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State machine의 VHDL code

2008.08.16 16:35

키큰기린 Views:2655 Recommend:33

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;

entity controlstatem is
        port (
                IR : in unsigned ( 1 downto 0 );
--                clk, inc, ld, clr : in bit;
                clk, inc, ld, clr : in std_logic;
                qout : out unsigned ( 3 downto 0 )
                );
end controlstatem;

architecture controlSM of controlstatem is
        signal q : unsigned ( 3 downto 0);
        
                
begin
        
        qout <= q;
        
        process (clk)
        begin
                if clk'event and clk = '1' then
                        if clr = '1' then        q <= "0000";
                        elsif ld = '1' then q <= '1' & IR & '0';
                        elsif inc = '1' then q <= q + 1;
                        end if;
                end if;
        end process;
        
end controlSM;